Switching Activity Based Method for Minimizing Testing Power in Digital Circuits
| Paper File | Download Paper File | | Appear In | ECTI Transaction EEC (ECTI Transaction EEC) | | Publication Date | 01/02/2007 - 28/02/2007 | | Volume | 5 | | Pages | 61 - 69 | | No | 1 | | Author 1 | Kuppusamy Paramasivam | | Author 2 | K Gunavathi |
Abstract
Optimization of testing power is a major signi¯-
cant task to be carried out in digital circuit design.
Low power VLSI circuits dissipate more power dur-
ing testing when compared with that of normal op-
eration. In this paper a novel method is proposed to
reduce the testing power and total energy by reorder-
ing the sequence of test vectors for minimum switch-
ing activity of the Circuit Under Test (CUT). Graph
theory concept is used to develop the reordering al-
gorithm which is based on heuristic approach to ¯nd
near optimal solution for the problem. Fault coverage
of the CUT is not a®ected in this algorithm. The re-
duction of power dissipation and total energy during
testing leads to increase in reliability of the circuit.
Experimental results of the proposed algorithm with
ISCAS85 benchmark circuits show that the switching
activity is reduced signi¯cantly compared to existing
works. |
