RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers
| Paper File | Download Paper File | | Appear In | ECTI Transaction EEC (ECTI Transaction EEC) | | Publication Date | 01/08/2008 - 28/08/2008 | | Volume | 6 | | Pages | 57 - 66 | | No | 2 | | Author 1 | Shahana T K | | Author 2 | Babita R Jose | | Author 3 | Rekha K James | | Author 4 | K Poulose Jacob | | Author 5 | Sreela Sasi |
Abstract
Current research on radio frequency transceivers
focuses on multi-standard architectures to attain
higher system capacities and data rates. Multiple
communication standards are made adaptable by per-
forming channel select filtering on chip at baseband
in digital domain. The computationally intensive
decimation filter in a sigma-delta analog-to-digital
converter plays an important role in channel selec-
tion for multi-mode systems. As these architectures
are targeted for portable applications, an area and
power e±cient reconfigurable implementation is an
implicit requirement. To this end, a multi-stage, pro-
grammable decimation filter based on residue num-
ber system &ecti_40;RNS&ecti_41; that is adaptable for WCDMA
and WLAN standards is presented in this research.
Multi-stage decimation filter implementation o®ers
low computational complexity and power dissipation.
The FIR filters of the multi-stage decimator operat-
ing in RNS domain o®ers high data rate because of
the carry free operations on smaller residues in par-
allel channels. Further power saving is achieved by
reconfiguring the hardware architecture, and power-
ing down the unused blocks in each mode of opera-
tion. For increased programmability modulo multi-
plication is performed by index addition utilizing the
arithmetic benefits associated with Galois field. Fi-
nally, a performance comparison of the proposed RNS
based decimation filter with traditional binary imple-
mentation is done in terms of area, critical path delay
and power dissipation. |
