A Compact 32-bit Architecture for an AES System
| Paper File | Download Paper File | | Appear In | ECTI Transaction CIT (ECTI Transaction CIT) | | Publication Date | 01/05/2005 - 31/05/2005 | | Volume | 1 | | Pages | 24 - 29 | | No | 1 | | Author 1 | Somsak Choomchuay | | Author 2 | Surapong Pongyupinpanich | | Author 3 | Somsanouk Pathumvanh |
Abstract
This paper describes a compact 32-bit architecture
developed for the Rijndael ciphering/decyphering
system. The implementation is complied with NIST
Advanced Encryption Standard (AES). The design
processes any 128-bit block data with 128-bit key. For
the compact hardware, the field inversion circuit and
the key scheduling circuits are shared by both the
encryption and decryption process. The on-the-fly
KeyScheduling implementation offers fast processing
speed but with core size trade-off. According to the
evaluation made on the targeted FPGA, the design
can offer the throughput of 768 mbps at 264 MHz
clock speed. |
